I’m currently a full professor (professore ordinario) at the University of Naples Federico II. I graduated in Electronics Engineering in 2003 and got a PhD degree in Computer Science in November 2006 from the same university. My main interests include digital design automation and custom hardware architectures, particularly for security-related operations. Specific topics include the application of high-level parallel programming paradigms to MPSoC design, the automated synthesis of complex on-chip interconnects, as well as novel hardware architectures implementing arithmetic functions and cryptographic primitives. (Take a look at my Research page for more details.)
I’m the single or main author of around 100 peer-reviewed papers published in leading scientific journals and conferences, such as IEEE Transactions on Computers, IEEE Transactions on Parallel and Distributed Systems, IEEE Transactions on Industrial Informatics, ACM Transactions on Architecture and Code Optimization, ACM Transactions on Embedded Systems, IEEE Transactions on Circuits and Systems-I, The Proceedings of the IEEE, IEEE Transactions on Information Forensics & Security, IEEE/IET Electronics Letters, DATE, VLSI-SoC, FPL, ITC conferences, and others.
I received a number of acknowledgments including the Intel HARP grant, the Altera Innovate Europe SoC Award 2015, the MBDA Innovation Award, the Simagine and eGate awards sponsored by Gemalto for innovative Smart Card applications. Earlier in my career I received the 2003 Federcomin-AICA Award for the best thesis in Italy in the field of Information and Communication Technology.
I’m involved in a number of research projects at both the national level (PRIN and STAR projects) and the European level (FP7, H2020, and HorizonEurope projects) in addition to a number of projects and contracts with industry. In particular, I’m currently serving as the Principal Investigator for University of Naples Federico II within the PNRR (EU Recovery Plan) Italian National Center on HPC, Big Data and Quantum Computing, Spoke 1: Future HPC. Within the Spoke, I proposed and currently leads WP4 “Trust and privacy”. I contributed to founding the National Laboratory on HPC Key Technologies and Tools (HPC-KTT), which aggregates the most representative national research groups in the area. Currently, I’m serving as the University of Naples representative in the laboratory.
I’m currently serving, or have served in the past, as an Associated Editor of IEEE Transactions on Circuits and Systems I: Regular Papers, IEEE Transactions on Circuits and Systems II: Express Briefs, Elsevier Microprocessors and Microsystems: Embedded Hardware Design, and Wiley/Hindawi Security and Communication Networks. (See my Editorial activities.)
I worked as an expert/reviewer for a number of national and international funding agencies. I’ve been serving as a chair/TPC member for numerous conferences and as a reviewer for countless scientific journals and conferences, including many IEEE and ACM transactions.
I’m a Senior Member of the IEEE, a member of the IEEE Industrial Society, and a member of the HiPEAC network.